A high-resolution all-digital phase-locked loop with its application to built-in speed grading for memory

Abstract

In this paper we present a high-resolution and wide-range all-digital phase-locked loop (ADPLL), which is suitable to function as a clock generator. The digitally controlled oscillator (DCO) is able to operate from 70 to 725 MHz and achieves 5.2ps resolution. The Phase-Frequency Detector (PFD) is designed using a latch-based sense amplifier, leading to a nearly perfect PFD that is able to resolve a phase difference as minute as only 1ps. In addition, we use this ADPLL as a vehicle to perform built-in speed grading (BISG) for memory. Combining a binary search process with multiple runs of built-in self-test (BIST), the maximum operating speed can thus be tracked down on the chip with a high precision. ©2008 IEEE.