0.6-V 2.1-mW RF receiver based on passive mixing and master-slave common-mode rejection technique in 65 nm CMOS

Abstract

A 0.6-V 2.1-mW RF receiver with regular threshold transistors is presented. A passive mixer which is built on low-power current-buffer is designed to build the RF front-end. A master-slave operational transconductance amplifier (OTA) structure which provides sufficient common-mode rejection ratio (CMRR) by auto-adjusting the gate of the triode-region biased tail current source is proposed as the building block of the intermediate-frequency (IF) modules. The proto-type of the RF receiver is designed and fabricated in Semiconductor Manufacturing International Corporation (SMIC) 65 nm CMOS process. The measurement indicates that the receiver covers a bandwidth from 1 to 1.5 GHz, achieving a voltage gain of 32 dB and a noise figure (NF) of 10 dB.