A performance optimization method by gate resizing based on statistical static timing analysis

Abstract

This paper discusses a gate resizing method for performance enhancement based on statistical static timing analysis. The proposed method focuses on timing uncertainties caused by local random fluctuation. Our method aims to remove botli over-design and under-design of a circuit, and realize highperformance and high-reliability LSI design. The effectiveness of our method is examined by G benchmark circuits. \Ve verify that our method can reduce the delay time further from the circuits optimized for minimizing the delay without the consideration of delay fluctuation.