FPGA implementation of random number generator using LFSR and scrambling algorithm for lightweight cryptography

Abstract

The IoT (Internet of Things) is a network of devices that are interconnected and are uniquely addressable, based on common communication protocols and links to perform certain tasks. The recent developments in the wireless communications have increased the need for the IoT-connected devices. The sensors and the sensor nodes used in these networks are low-resource devices, thus increasing the vulnerability and hence becoming a possible target for hackers. The development and deployment of lightweight protection schemes for such low resource devices have also increased. The random number generation or the key generation used in the encryption process is the most important element in protecting these resource-constrained devices, as the security of the entire data depends on the key used. In this paper a novel random number generation using LFSR (Linear Feedback Shift Register) and Scrambling Algorithm for lightweight encryption algorithms is proposed using which the keys for the encryption process can be generated, thus improving the security of data transmitted in the IoT environment. The randomness of the numbers generated by this Random number generator algorithm is tested using pertinent set of statistical tests. These statistical tests analyze the cryptographic properties of the sub keys generated by the key scheduling algorithm, such as confusion, diffusion, independence, and randomness. For the purpose of simulation, the code is written in Verilog and simulated using Xilinx Vivado and the implementation is carried out using Artix-7 FPGA family for analyzing the parameters like Area, power and timing.